1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor memory device with an internal clock generating circuit embedded therein. More particularly, the present invention relates to a configuration of a clock generating circuit for generating a clock signal used for producing an internal voltage or for determining an internal timing in a non-volatile memory such as a flash EEPROM (electrically erasable and programmable read only memory).
2. Description of the Background Art
FIG. 23 is a diagram schematically showing an overall configuration of a flash EEPROM as an example of a conventional semiconductor integrated circuit device. Referring to FIG. 23, the semiconductor integrated circuit device includes: a memory array 900 having a plurality of non-volatile memory cells arranged in rows and columns; an X decoder 901 for selecting an addressed row in the memory array 900; a Y decoder 902 for selecting an addressed column in the memory array 900; and a source/well decoder 903 for selecting a source line and a well (substrate) region in the memory array 900. In a data write (program)/erasure operation of a non-volatile memory cell, a voltage for write (program) or erasure is applied on a source, a gate and a substrate region of a selected non-volatile memory cell. The source/well decoder 903 selects a source line and a well region onto which the voltages necessary for the write (program: simply referred to write hereinafter)/erasure are applied.
The semiconductor integrated circuit device further includes: an address buffer 904 receiving an external address signal to generate an internal address signal based on the received external address signal depending on an operating mode; a write circuit/sense amplifier 905 for performing write/read of data; and a data buffer 906 for performing external input/output of data.
The address buffer 904, in a normal data read mode, generates an internal address signal according to external address input to generate an internal address signal to the X decoder 901, the Y decoder 902, and the source/well decoder 903. In a write/erase mode, the address buffer 904 selects address signals sequentially generated internally according to an external address to apply the selected address signals to the decoders 901 to 903.
The write circuit/sense amplifier 905 includes: a write register circuit for sequentially storing write data received from a data input buffer included in the data buffer 906 in data write operation mode; and an external read sense amplifier for amplifying memory cell data read out from memory cells selected by the Y decoder 902 to apply the amplified data to a data output circuit included in the data buffer 906 in data read operation mode. The write circuit/sense amplifier 905 may include an internal read sense amplifier for internally reading out data for verification of write/erasure.
The semiconductor integrated circuit further includes: a write/erase control circuit 909 capturing an external command to generate internal control signals necessary in a specified operating mode under control of a control signal; a high voltage generating circuit 908 for generating a high voltage (a positive or negative high voltage) necessary in write/erase operation under control of the write/erase control circuit 909; and a ring oscillator circuit 907 performing an oscillating operation under control of the write/erase control circuit 909 to generate a clock signal providing an operation timing for the write/erase control circuit 909 and being used in a high voltage generating operation of the high voltage generating circuit 908.
The write/erase control circuit 909 determines whether an effective (valid) command is applied according to a specific control signal, such as a write enable signal /WE, to generate necessary control signals according to an operating mode specified by the effective command, for controlling the operations of the decoders 901 to 903, the address buffer 904, the write circuit/sense amplifier 905 and the data buffer 906.
The address buffer 904 takes in an external address when an external control signal instructs that the semiconductor integrated circuit device is selected. The data buffer 906 also performs buffering of data read out by the write circuit/sense amplifier 905 to output the buffered data externally when the external control signal instructs data read.
In the semiconductor integrated circuit shown in FIG. 23, the ring oscillator circuit 907 performs an oscillating operation in a predetermined oscillating period to generate a master clock signal providing an operating timing of the write/erase control circuit 909 and further generates a pump clock signal necessary for a charge pump operation of the high voltage generating circuit 908 normally constituted of a charge pump circuit. Hence, in the ring oscillator circuit 907, there are individually provided a circuit for generating a master clock signal and a circuit for generating a charge pumping clock signal.
With such ring oscillator circuit 907 provided internally, the number of pin terminals decreases and there is no need to drive an on-board interconnection line for transmitting an external clock signal, when compared with a configuration to which the external clock signal is applied, and the power consumption of the entire system is reduced. By operating the write/erasure control circuit 909 in synchronization with the master clock signal from the ring oscillator circuit 907, various kinds of internal operation timings can be determined on the basis of the master clock signal, thereby enabling accurate setting of the internal timings.
FIG. 24 is a diagram representing an example of the configuration of a ring oscillator included in the ring oscillator circuit 907 shown in FIG. 23. In FIG. 24, the ring oscillator circuit 907 includes: inverter chain including cascaded inverters IVa of (2nxe2x88x921) stages; and an inverter IVb inverting an output signal from the last stage of the inverter chain to generate an output signal xcfx86OUT (clock signal).
The ring oscillator is constituted of the inverter chain including inverters IVa of an odd number of cascaded stages. In a case where an oscillating circuit is constituted of such inverter chain, a CMOS inverter formed of a P channel MOS transistor (an insulated gate field effect transistors) and an N channel MOS transistor is generally employed as each inverter IVa of the inverter chain and the inverter IVb.
In such a CMOS inverter, an operating characteristic of a MOS transistor has a temperature dependency. That is, in a MOS transistor, as temperature rises, each mobility of electrons and holes in a channel is made smaller (due to increased lattice vibration and/or lattice scattering), and thereby, a drain current Ids decreases. Hence, the operating characteristics of the CMOS inverter chain has such a temperature dependency that, charging and discharging speeds become faster as temperature falls and an oscillating period of the ring oscillator become shorter, while as temperature rises, the charging and discharging speeds of the inverter chain formed of inverters IVa becomes slower and an oscillating period thereof becomes longer.
FIG. 25 is a diagram representing an example of the configuration of the high voltage generating circuit 908 shown in FIG. 23. In FIG. 25, the high voltage generating circuit 908 includes a charge pump 908a for generating a high voltage VP according to an output signal xcfx86OUT of a ring oscillator 907a included in the ring oscillator circuit 907. The charge pump 908a utilizes a capacitor to perform a charge pump operation according to the output signal xcfx86OUT of the ring oscillator 907a for generating the high voltage VP. The high voltage generated by the high voltage generating circuit 908 may be a negative voltage. Even in a case of a high voltage of the negative polarity, a negative high voltage is generated through a charge pump operation. Now, it is assumed that the high voltage VP is a positive voltage.
In the charge pump 908a, an amount of electric charges transferred by a one time pump operation is proportional to a product of a capacitance value of the capacitor used in the charge pump 908a and a frequency of the output signal xcfx86OUT of the ring oscillator 907a. Therefore, when an oscillating cycle period becomes longer and a frequency of the pumping clock signal xcfx86OUT becomes lower, a pumping capability of the charge pump 908a decreases, thereby disabling setting of the high voltage VP to an intended voltage level.
Conversely, as temperature decreases, the oscillating period of the ring oscillator 907a becomes shorter, a frequency of the output signal xcfx86OUT thereof becomes higher, a pumping capability of the charge pump 908a becomes higher and power is unnecessarily consumed to increase the power consumption.
That is, a positive high voltage VP or a negative high voltage VB generated by the high voltage generating circuit 908 comes to have temperature dependency as shown in FIG. 26. That is, the positive high voltage VP has a negative temperature dependency, while the negative high voltage VB has a positive temperature dependency. In general, operating conditions are set, based on the premise that the positive and negative high voltages VP and VB satisfy the respective design values VPR and VBR.
In a non-volatile memory, a memory cell is constituted of a stacked gate MOS transistor having a control gate and a floating gate. Write and erasure are achieved by shifting a threshold voltage of the memory cell transistor through injection/ejection of electric charges into/from the floating gate. While a write and erasure states of a memory cell are different depending on a memory cell configuration, the high voltages VP and/or VB are applied to a prescribed region of a memory cell transistor such that migration of electrons arises to or from the floating gate in the write/erasure operation. In a case where the absolute values of the high voltages VP and VB are smaller than prescribed values VPR and |VBR|, respectively, migration of a sufficient amount of electric charges does not occur, and therefore, no correct write/erasure can be performed. In general, a verification operation is performed in the write/erasure and there is an opportunity where such erroneous determination is made that the write/erasure is incomplete.
In a case where temperature is low, the high voltages VP and VB could be normally set so as to assume respective prescribed values by a level detecting circuit. Therefore, a problem of such defective write/erasure may hardly occur. However, since the charge pump circuit 908a comes to have an increased pumping capability, a current more than necessity is consumed, resulting in a problem of an increase in consumed current.
Furthermore, in a case where an output signal of the ring oscillator in the ring oscillator circuit 907 is used as a master clock for the write/erasure control circuit 909, a frequency of the master clock signal has a temperature dependency, an internal operation timing varies depending on temperature, and a timing margin of an internal operation varies over a wide operating temperature range. Therefore, a problem arises that a stable operation cannot be ensured
Accordingly, in a case where a ring oscillator circuit is provided in the semiconductor memory device and a clock signal is generated internally, to perform generation of a necessary internal voltage and determination of an internal timing, there arises a problem that a stable clock signal can not be supplied over a wide range of an operating temperature of the semiconductor memory device.
In general, a ring oscillator circuit having a temperature detection function of performing temperature compensation for eliminating such a temperature dependency is provided separately on a system board and a clock signal is supplied from the outside of the semiconductor memory device, resulting in a problem of increase in number of terminals and chip area of the semiconductor memory device. Furthermore, in a case where a clock signal is generated by an external ring oscillator circuit on a system board, an on-board wire is necessary to be driven, leading to a problem that a consumed current as a whole increases. Thus, such a problem arises that an advantage of a semiconductor memory device with an internal clock generating clock is lost, and a mounting area of the entire system is also increased.
It is an object of the present invention to provide a semiconductor integrated circuit device having an internal clock generating circuit capable of stably supplying a clock signal over a wide range of operating temperature.
It is another object of the present invention to provide a clock generating circuit suited for integration and capable of stably generating a clock signal over a wide range of operating temperature.
It is still another object of the present invention to provide an internal clock generating circuit capable of stably supplying a clock signal used in a non-volatile memory.
A semiconductor integrated circuit device according to the present invention includes: a memory circuit for storing data; a clock generating circuit for generating a clock signal used by the memory circuit; a temperature detecting circuit; and a cycle change circuit for changing a cycle of a clock signal generated by the clock generating circuit according to a detection output signal of the temperature detecting circuit.
A semiconductor integrated circuit device according to another aspect of the present invention includes: a memory circuit for storing data; a temperature detecting circuit, integrated together with the memory circuit on a common semiconductor substrate, for detecting temperature; and a clock generating circuit, integrated together with the memory circuit on the common semiconductor substrate, for generating a clock signal having a cycle thereof changed according to an output signal of the temperature detecting circuit. The clock signal is used in the memory circuit.
By providing an on-chip temperature detecting function for performing temperature compensation on a clock signal, there is no necessity to provide a temperature detecting circuit on a board, thereby enabling a system mounting area on the board to decrease.
Since temperature detection and clock generation are performed in the inside of a semiconductor integrated circuit device, power consumption of the entire system can be reduced and furthermore, there is no necessity to provide an extra terminal for temperature detection or for a clock signal input to a semiconductor integrated circuit, thereby allowing a chip area to decrease.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.